1. Field of the Invention
The present invention relates to chip carriers and, more particularly, to high density chip carriers with improved performance for use with flip chip technology, and the like.
2. Background and Related Art
As the terminal density of semiconductor chips and, particularly, the density of Input/Output (I/O) connections of chips increases with improved technology, the wireability of chip carriers becomes more problematic. The density of terminal pads tightly clustered makes it difficult to construct mutually segregated conductors to connect carrier lines to each terminal pads. Signal carrying terminal pads and lines are particularly burdensome since they must be segregated from each other as well as from power and ground lines. Signal lines on the chip carrier must have sufficient electrical isolation from other conductors so that undesired coupling and leakage paths are avoided.
To enable routing in highly dense chip carriers, microvia, as well as other technologies, have been developed. Microvia chip carriers typically use multiple layers to make the required interconnections, particularly in chip packages using flip-chip ball grid array (BGA) technology. In these high pin count technologies, the density of wiring and the wireability of the layers is important, particularly in terms of cost, yield, performance and reliability. “Wireability”, in this regard, can be viewed as the technical possibility of positioning routing lines so that all signals may “escape” (inward or outward) from a given pattern or layer. Constraint considerations for routing include via density, routing line widths and clearances, the terminal pad sizes and required clearances, the shielding requirements and other design constraints known in the art.
Microvia chip carrier substrates are generally built around a core with plated thru holes (PTHs). Such high density interconnect (HDI) chip carriers use build-up of layers on each side of a core made of epoxy-glass layers. The glass layers are made of a glass cloth impregnated with epoxy and are laminated at elevated temperatures to make a solid, dimentionally stable core. The build up layers on each side of the core are generally non-reinforced epoxy. An example of a typical microvia chip carrier is that described in U.S. Pat. No. 6,518,516 B2
In chip carriers, such as microvia chip carriers, density constraints and limited space for PTHs under the chip limit the vertical interconnection capability between the front (chip side) and back (board side) of the carrier. This is a particular problem with regard to the power distribution requirements for higher I/O count, higher power chips. Fanout wiring requirements in the signal distribution layers necessarily limit the amount of space remaining in the middle of the chip for power distribution. As a result, the limited number of PTHs that can be accommodated in the remaining middle region under the chip causes poor power distribution characteristics and power related noise.
Although other solutions to these problems exist, such solutions have other drawbacks. For example, ceramic chip carriers and teflon-based chip carriers have been employed to provide improved power distribution but, these solutions are significantly more expensive. In addition, ceramic chip carriers have reliability problems at the interconnection of chip carrier and printed wiring board (PWB). Teflon-based carriers also have limited flexibility in terms of layer counts and wireability.